With the deceleration of Moore’s law, the semiconductor industry has to find new ways, besides just scaling the transistor, to continue PPACt optimization for different applications and verticals.
This requires turning different knobs via innovations in materials, processes, transistor device architectures, design architectures, packaging and systems. MSCO extends traditional DTCO for these innovations via fast, iterative, virtual learning cycles that can tune multiple knobs simultaneously for cost-effective and informed trade-offs in PPACt. Sage DA tools are a critical part of this rapid PPACt analysis in the MSCO platform.
Design Rule Compiler
Faster, verifiable and easy-to-use path from design rule intent to DRC decks
DRC Runset Validation
Enabling fast, first-time-correct DRC decks for new process technologies
Contact us to learn how Sage Design Automation can help you accelerate design enablement for new process technologies.