Chip Design: iDRM From Sage-DA

Posted on: June 7th, 2013

By Hamilton Carter

Coby Zelnik president, and CEO of Sage-DA gave me a quick primer on the flow from a newly defined fab process and its design rule manual, (DRM), to a completed design rule check, (DRC), deck yesterday. While this flow lies on the opposite end of the chip design abstraction spectrum from my normal haunt, (functional verification), it turns out one of the major challenges is exactly the same: how can you be sure that a subjectively written specification, (in this case, the design rule manual), is properly implemented in the form of a DRC deck with concrete meaning?

Sage-DA is presenting their answer to the challenge in the form of iDRM. While DRCs used to be the sole domain of a handful of experts who translated the DRM into specialized programming languages. iDRM enables any engineer to quickly enter design rule checks by specifying component size, spacing, and orientation in an easy to use graphical interface. Once the mini-layout related to a design rule is specified, then the designer can specify the rule itself using logical assertions. These newly created design rules can be used in a number of ways.

Quick DRM Intent Checks

As I mentioned above, it turns out that DRMs, suffer from the exact same issue as functional specifications: the author said it, but did they mean it? By running design rules defined in iDRM against sample layouts provided by the fab, an engineer can quickly check whether or not their new rule behaves correctly. They can then close the interpretation loop quickly with the author of the DRM using iDRM’s failing testcase and graphically defined rule to facilitate communication and arrive at an agreed upon, concrete interpretation for the design rule in question.

Test Case Generation

iDRM can also generate passing and failing testcases for newly defined design rule checks. These generated test suites can be used to check the correctness and completeness of third party DRC decks.

Rapid Internal DRC Authoring and Early Deployment

Using the fab’s DRM is a must, but it won’t differentiate you from your competition. Many companies augment the fab’s DRM with their own design rule checks tailored for the performance enhancements a specific product requires, such as speed, power, or area. By entering concrete and verifiable design rules early in the project using iDRM, the design team is able to check their nascent blocks well before full chip integration when design rule violations can cause costly project-wide delays.

Physical Data Mining

It’s not enough to define checks and testcases, you have to know what was actually checked on your design and how. In the functional verification world, we call this coverage and Sage-DA’s iDRM tool addresses this area as well. iDRM can scan your layout and provide data regarding where each DRC was executed on the chip. In addition to providing coverage of which checks were triggered by your layout, iDRM can also generate histograms for each DRC indicating the range of physical parameters, (such as trace width and separation), that were used in the check.

iDRM Modern DRC Verification Delivered

While the worlds of functional and physical verification may seem vastly different, at the end of the day they share the same challenge, the subjective nature of interpretation between specification and implementation. iDRM helps companies rise to the challenge by applying the verification triumvirate of automated test generation, check execution, and coverage collection, long time bastions of the functional verification world, to the physical verification process.

Article on Chip Design


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