EE Times: Sage solving an orphan EDA problem

Posted on: May 7th, 2013

By Brian Bailey

Many aspects of the design, verification and manufacturing flows that we use today have evolved over time. Would we have done them that way had we known where it would lead? In many cases probably not, but there was no reasonable way to tell back then, when things got started, what the trajectory would be. Today, some of those issues have become quite acute and yet there is no incentive for anyone to fix them. Why? Because too few people have the problem and so fixing it is uneconomic. It is a similar situation with orphan drugs. There would be no way to recoup the cost of development, trials and education while charging a realistic price for the drugs because too few people have the disease. Sage Design Automation believes they have identified one of those cases with the EDA world, but they believe they have a way to make it pay. They believe that once a real solution has been put in place it will become useful for a whole new class of problems and so the potential user base will be expanded to the point where it does become economic.

Let us return to the problem first. Sage defines it this way: Design rules are written by fab process engineers and reflect the fabrication limitations for each drawn layer or combination of layers. Design rules are captured in the Design Rule Manual (DRM). The DRM book, published by the foundry, represent a contract between the fab (or foundry) and the design house: if the designers keep all physical design features “legal” according to the DRM description, the resulting device can be fabricated successfully with good yield.

sage fig 1

Designers want to make the design as compact as they possibly can but at the same time, they have to conform to the rules and they check this by running Design Rules Checker (DRC). This is a tool that runs a DRC Deck. But where does that deck come from? This is where the problem starts. The DRM is written by process people in the fabrication houses in free form English to describe the geometric limitations of shapes and is often ambiguous and incomplete. An EDA person then has to try and work out what the process engineer meant and write the rule in a way that a tool can execute it. This was not a huge problem when the number of rules was small and the complexity of them simple, but today neither of these statements are true. This creates a lot of work and uncertainty and means that the DRC deck does not stabilize for quite some time.

With the problem stated, you can perhaps now see the reason why I called it an orphan. The only people who would buy a tool to fix this problem are the fabs and we all know that the number of those is extremely limited. However, this was the initial problem that needed to be solved and Sage has done this by creating a formal, graphical design rule capture tool. They call it iDRM and it enables the rules to be captured and verified. The figure below shows the rule as it would be written today on the left. In the middle is the graphic representation as captured within iDRM. This rule can then be applied to a sample layout and it will show what passes and what fails the rule. In this way, the process engineer was verify that the rule is doing exactly what they meant it to do and thus they now have a very tight debug iteration loop so that when the DRM is published to the EDA companies the semantics are clear and will avoid them having to go around the debug loop with the fab.

But how will Sage make money? The fab only cares about rules that will ensure yield, but a design house actually has to worry about getting the right balance between performance, power and area and that requires paying attention at the layout level. They will be concerned about where contacts are placed, distance between things etc. Sage believes that by giving design houses the ability to quickly and easily create their own rules, they will have expanded the market into something large enough to make a viable business for them and provide a tool that will enable the design houses to squeeze more performance out of their silicon. Sage calls these additional rules Design Quality Checks. These do not have to be on the latest technology nodes and in fact this makes them one of the primary sales targets because most of the fabs have already produced the initial DRM for 20nm and are working on 14nm today. Such a tool can also be used for data mining so that, for example, the number of occurrences of certain rules can be found or the locations of them.

sage fig 3

Article on EE Times


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