News

Sage-DA at DAC in  Las Vegas,
June 3-5, booth #832

Posted on: May 21st, 2019

Accelerating the Path from
Process Technology to Physical Design

NEW: SLiC - a brand new library layout generation tool

Join Sage at DAC 2019 booth # 832 and take a sneak peek at this game changing new technology

SLiC (Standardcell Library Compiler) generates DRC correct and optimized cell layouts from netlists. Users can define devices and cell architectures to create different types of libraries, and also set different optimization goals. SLiC targets the latest and next technology nodes (≤10nm) and takes only one day (including technology and architecture setup) to generate a complete library. The speed and ease-of-use make SLiC ideal for fast path-finding and DTCO (Design Technology Co-Optimization) iterations using a large, representative set of production quality cells.

Design rule development system

We will also present and demonstrate:

DRVerify: Validation and QA of DRC runsets

With today's complex process technologies, DRC runset errors are often very hard to detect and undetected runset errors can create escapes for critical mask and silicon defects. DRVerify addresses this problem by thoroughly testing DRC runsets and making sure they are correct and accurate. DRVerify automatically generates a QA set of passing and failing layout test cases for each design rule. The tool analyzes the results of the DRC run on the QA test set and provides a consolidated summary as well as detailed information for each discrepancy found.

iDRM: integrated Design Rule Management system

The iDRM system integrates design rule development, documentation, visualization, enforcement and validation all in one tool set. iDRM integrates unique features including reading and synchronizing existing design rule spreadsheets, quick interactive design rule checker and automatic QA of signoff DRC decks. iDRM is pattern based and can be used to search, analyze and profile designs for different patterns, connectivity and additional geometrical and electrical properties.

DTCO: Design Technology Co-Optimization

Combined together, iDRM and SLiC enable users to explore different process assumptions and rule values, try different "what-if" scenarios and analyze interactions and trade-offs between technology constraints and design considerations. Engineers can quickly create logic libraries, use them to implement logic blocks, and run DRC to make sure the design is consistent and correct.


 Sign up for a demo and discussion with our experts!

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