News

Sage-DA at, DAC in San Francisco,
June 7-11, booth #1924

Posted on: May 22nd, 2015

How good is your DRC deck?

This year we will present our latest solution for DRC deck validation. Visit our booth and check out all the new capabilities and benefits enabled by the design rule compiler. iDRM supports the latest process node rules including 10nm.

- Sign up here for a demo -

What to see this year:

  • DRC deck verification and QA
    Automatically create QA pass/fail tests for verifying any DRC deck
    DRVerify automatically creates rigorous and accurate pass/fail tests for 3rd party DRC deck validation. These layout test cases are then used to verify the completeness and accuracy of your DRC deck.
  • Failure analysis
    Correlate hotspots with specific layout configurations and parameters
    Profile your layout in order to correlate hot spot results with layout topologies and parameters.
  • Layout data-mining and analysis
    Explore and communicate what is actually in your design
    Gather measurements and statistics for all instances of: specific design rules, sensitive patterns, device physical characteristics, layout dependent effects, DFM rules, etc. Auto-generate a complete report with all details, coordinates, tables & screen shots in seconds.
  • Technology for the latest design rules
    Supporting the new challenges of advanced nodes (10nm included)
    Supporting the latest design rule challenges such as triple coloring, density balancing, stitching, connectivity and more.
  • Custom design rule checks
    Add methodology rules and checks supplementing the foundry DRC deck
    Create rules representing best design practices that ensure quality of design, optimal performance, and minimized variability can be added easily and graphically.


 - Sign up here for a demo -

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