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EE Journal: Testing our the rules

Posted on: April 22nd, 2013

By Bryon Moyer

It wasn’t too long ago that we took a look at a new tool from Sage DA that could be used to create design rules in an automated fashion so that the resulting rules will be clean and consistent. It also provided a way to iron out any ambiguities in a design rule manual.

For those of you less deeply embedded in this space, what we’re talking about here is the ability to check a new chip design’s layout to make sure it doesn’t violate manufacturing rules. In order to be able to do that, we need to have a set of rules to test whether a specific IC meets the constraints of a given process. That way you ensure that no lines are too thin or spaces too narrow. (Oi, if only it were that simple.)

This Design Rule Check (DRC) happens before you bless a set of masks for production. But before you can do the tests, you have to figure out what ...

Click here to read the full article on eejournal.com

 

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