News

SemiWiki:
Design Rule Development Platform @DAC

Posted on: June 15th, 2017

By Daniel Nenni

While some might have expected the exponential growth in design rules number and complexity to cool down a little, it looks as if these are only heating up more. The multiplicity of technology nodes, lithography options, fundamental technology options (Bulk, FD-SOI, FinFET), different process flavors and specific applications, have made design enablement and design rules in particular an even more painful issue than it used to be.

Sage-DA addresses this problem in a systematic way with iDRM, a complete end-to-end ...

Read the full article on SemiWiki.com!


"OPAL: A High-Level Design Rule Modeling Language"
Sage-DA on an industry experts panel at DAC

Posted on: June 8th, 2017

A panel of industry experts
June 19 11:00 AM Austin Convention Center - Room 7

Discover the powerful capabilities of OPAL, a high-level, declarative language for 2D pattern recognition and analysis. OPAL’s geometric expressions can accurately and concisely describe user-specific layout constraints of any complexity.

Join a team of industry experts that will present and discuss this exciting new capability, while you enjoy a complementary lunch at DAC.

Click here for more details.



DAC 2016
Sage-DA will exhibit at DAC Austin,
June 18-22, booth #513

Posted on: June 8th, 2017

Sage-DA will demonstrate the complete iDRM design rule development and automation system, featuring:

  • Design rule capture
  • Electronic DRM
  • Interactive built-in DRC
  • Compiled DRC deck
  • DRC deck verification and coverage
  • Design Rule Extraction from existing layout
  • Pattern extraction and classification

Read more or Sign up for a demo



Sage is on GSEDA "Must See at DAC" list
Posted on: June 6th, 2016

Must See DAC

GSEDA’s “Must See” list


SemiWiki:
iDRM - A Complete Design Rule Development System

Posted on: June 4th, 2016

By Daniel Nenni

Design rules are at the heart of the interface between the foundry and semiconductor designers, which makes them so critical. Traditionally, design rules and DRC decks have been developed manually with no or little automation. Design rule definitions are written using WORD or other general purpose office tools, and DRC decks are programmed in an attempt to match that text definitions. This state of affairs leaves many challenges, such as:

  • How do you verify that the DRM (design rule manual) rule definition accurately represents the rule intent?
  • How do you ensure the definition is complete and unambiguous?
  • How do you verify that the DRC code exactly matches the DRM definition?

So far, there have not been good solutions to these challenges, which resulted in ...

Read the full article on SemiWiki.com!



"The insanity of DRC rules and DFM at 10nm"
Sage-DA on an industry experts panel at DAC

Posted on: May 30th, 2016

A panel hosted by Si2 at DAC  June 6  11:00 am  Si2 booth 239

In just over 10 years, process nodes will shrink from 100nm in 2005 to 10nm in 2017. An upsurge in the complexity of advanced DRC decks makes it almost impossible to code rule decks using basic Pass/Fail DRC rules. The exponential increase in the design rule count and the number of operations required by complex DRC rules has made physical verification run times longer and increases debug times. A panel of four industry experts representing design, implementation, verification and manufacturing will describe their own personal experiences and best practices for developing DRC decks for 10nm processes.

Click here for more details.



DAC 2016
Sage-DA will exhibit at DAC Austin,
June 5-9, booth #421

Posted on: May 19th, 2016

Sage-DA will demonstrate a complete design rule development system with the following functions:

  • Design rule capture
  • DRC reference
  • -NEW- Electronic DRM
  • -NEW- Compiled DRC deck:
  • DRC deck verification and coverage
  • -NEW-Design Rule Extraction from existing layout
  • -NEW- Pattern extraction and classification

Read more or Sign up for a demo



Sage-DA to exhibit in SPIE Advanced Lithography, San Jose  February 23-24
Posted on: February 10th, 2016
DAC 2014



EDACafe:
Camposano & Zelnik: Sage-DA promotes EDA Evangelism

Posted on: August 27th, 2015

Blogs are a dime-a-dozen, but you’re going to want to read this one if you want to know why distinguished veterans of EDA continue to evangelize for the viability and vitality of the industry.

On a phone call this week with Raul Camposano, newly-minted CEO of Sage Design Automation, and Coby Zelnik, President and Co-founder of the company, the point was driven home repeatedly: There’s as much of a future in EDA as there is a past, no matter what the current demographics may imply. Evolving demand in the CAD-tool marketplace means EDA companies will continue to emerge to meet that demand.

Click here to read the full article on edacafe.com



Dr. Raul Camposano Joins Sage-DA as CEO
Posted on: August 17th, 2015

Dr. Raul Camposano Joins Sage Design Automation as Chief Executive Officer
 
Company expands next generation physical verification solutions

August 17, 2015, Santa Clara, California –  Sage Design Automation Inc., the company that is redefining physical verification, announced today the appointment of Dr. Raul Camposano as its Chief Executive Officer. 

Dr. Camposano has had a distinguished... Read more



EDN takes notice of Sage-DA at DAC
Posted on: June 11th, 2015

"Sage Design Automaton's iDRM addresses the pain points re DRC creation and verification at advanced process nodes. The number and complexity of rules has arguably become unmanageable, and this looks like a solution".

Click here to see the article on EDN.com.



EETimes: Can you trust a DR-Check without a DR-Spec?
Posted on:

Designers may find the flow from the design rule specification tool to the design rule check tool to be surprising (spoiler: there is no design rule specification tool).

The cornerstone of physical verification is DRC (design rule checking): checking that the design adheres to the technology design rules. As we all know, DRC has become ...

Click here to see the article on EETimes SoC Designline‏.



SemiWiki: How good is your DRC deck?
Posted on:

By Daniel Nenni

Design Rule Check (DRC) is the #1 foundry sign-off check. Fabless companies receive the DRC deck from the foundry; it's a file comprising thousands of commands in a proprietary checker language for a specific DRC tool. In advanced technologies such a deck executes tens of thousands of geometric operations on the physical design data as it tries to detect ...

Click here to read the full article on SemiWiki.com



Sage-DA will exhibit at DAC San Francisco,
June 7-11, booth #1924

Posted on: May 22nd, 2015

DAC 2015


Sage-DA to present at ISPD , Monterey, CA
March 29 - April 1

Posted on:

Sage-DA will present a paper at the International Symposium for Physical Design. The paper title is: “Design Rule Management and its Applications in 15nm FreePDK Technology”. It will be presented as part of the 15nm FreePDK session on Wednesday April 1.

Click here to view the website of ISPD.



Sage-DA to exhibit in SPIE Advanced Lithography, San Jose  February 24-25
Posted on: January 19th, 2015
DAC 2014



Semiconductor Engineering:
Design Rules Explode At New Nodes (Part 3)
Posted on:

Experts at the table, part 3: The fuzzy relationship between EUV and design rules; bending rules for new shapes and structures becomes harder at advanced nodes.

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at GlobalFoundries; Michael White, director of product marketing for Calibre Physical Verification at Mentor Graphics, and Coby Zelnik, CEO of Sage Design Automation. What follows are excerpts of that roundtable discussion. ...

Click here to read the full article on semiengineering.com



Semiconductor Engineering:
Design Rules Explode At New Nodes (Part 2)
Posted on:

Experts at the table, part 2: Speeding up time to market; finFETs vs. 2.5D; partitioning designs; bounding complex problems with rules; better supply chain communication.

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at GlobalFoundries; Michael White, director of product marketing for Calibre Physical Verification at Mentor Graphics, and Coby Zelnik, CEO of Sage Design Automation. What follows are excerpts of that roundtable discussion. ...

Click here to read the full article on semiengineering.com



Semiconductor Engineering:
Design Rules Explode At New Nodes
Posted on:

Experts at the table, part 1: The number and complexity of rules has been increasing since 28nm. Whose problem is it to solve? Plus, training and capabilities vary greatly across teams within the same companies.

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at GlobalFoundries; Michael White, director of product marketing for Calibre Physical Verification at Mentor Graphics, and Coby Zelnik, CEO of Sage Design Automation. ...

Click here to read the full article on semiengineering.com



SemiWiki: DRM to PDK automatic update at DAC
Posted on: May 29th, 2014

... At DAC, Sage-DA will demonstrate how PDK parameters for generating parametrized cells (Pcells) can be automatically created and updated from the iDRM design rule source. The iDRM platform can thus be used as a single point of entry for design rules enabling consistency and accuracy across a broad array of EDA tools and flows. ...

Click here to read the full article on SemiWiki.com



Sage is on GSEDA "Must See at DAC" list for the 2nd year
Posted on: May 28th, 2014

Must See DAC

GSEDA’s “Must See” list
Sage-DA will exhibit at DAC San Francisco,
June 2-4, booth #1423

Posted on: May 20th, 2014
DAC 2014

EE Journal: Testing our the rules
Posted on: April 22nd, 2014

It wasn’t too long ago that we took a look at a new tool from Sage DA that could be used to create design rules in an automated fashion so that the resulting rules will be clean and consistent. It also provided a way to iron out any ambiguities in a design rule manual.

For those of you less deeply embedded in this space, what we’re talking about here is the ability to check a new chip design’s layout to make sure it doesn’t violate...

Click here to read the full article on eejournal.com


EDACafe: Automating rule checking
Posted on: March 31st, 2014

If ever there was a need for additional help in design, now is the time. As the industry marches down, node after node, the problems ramp up, node after node. After my conversation with Mentor’s Joe Sawicki several weeks ago about all of the pros/cons of moving to the next node, it was good then to speak with Sage-DA CEO Coby Zelnik about...

Click here to read the full article on edacafe.com


EE Times Europe covers DRVerify
Sage Design Automation’ DRVerify is a new tool that verifies design rule check (DRC) decks. Used by process design kit (PDK) teams and DRC deck developers, DRVerify addresses the problem of DRC deck errors, especially...

Click here to read the full article on electronics-eetimes.com


Sage-DA joins the eBeam Initiative

Ckick here to read the article on eBeam.org


Sage-DA to exhibit in SPIE Advanced Lithography,
San Jose February 25-26

SPIE

Press Release: Sage-DA announces a tool to verify DRC decks
Posted on: February 18th, 2014

DRVerify acts like ATPG for DRC, targeting complex new process design rules February 18, 2014, Santa Clara CA – Sage Design Automation, Inc. (Santa Clara CA) today announced DRVerify, a new tool that verifies design rule check (DRC) decks – the latest product in the iDRM design rule compiler platform… Read more


SemiWiki: iDRM for Complex Layout Searches and IP Protection!
Posted on:
February 6th, 2014

iDRM (integrated design rule manager) from Sage-DA is the world's first and only design rule compiler. As such it is used to develop and capture design rules graphically, and can be used by non-programmers to quickly capture very complex and shape dependent design rules and immediately generate a check for them. The tool ...

Click here to read the full article on SemiWiki.com


EDACafe: Design Rule Manual Creation a Bottleneck
Posted on:
June 24th, 2013

Sage Design Automation, Inc. announced its founding technology last month and created a lot of customer and media buzz at DAC’13 in Austin. I bet a lot of people were surprised that design rule manual creation and DRC deck implementation were manual, error-prone tasks – especially as we get into smaller process geometries – and that they can take years to put one together.

In a way, it’s a lot like writing a long paper on a typewriter, or even by hand. When you make an error, you...

Click here to read the full article on edacafe.com


EE Journal: A Clean-By-Construction Deck
Posted on: June 20th, 2013

Sage Introduces a DRC Compiler by Bryon Moyer So you’ve spent many months on a chip design project that’s winding down. Layout is done, or at least you hope it’s done, and it’s time to make sure that you did it right. (Yes, I know… most designs today will involve many people doing different things,…

Click here to read the full article on eejournal.com


Chip Design: iDRM From Sage-DA
Posted on: June 7th, 2013

Coby Zelnik president, and CEO of Sage-DA gave me a quick primer on the flow from a newly defined fab process and its design rule manual, (DRM), to a completed design rule check, (DRC), deck yesterday. While this flow lies on the opposite end of the chip design abstraction spectrum from my…

Click here to read the full article chipdesignmag.com


iDRM is #1 on Semiwiki must see at DAC list
Read Full artcile on SemiWiki
iDRM on GSEDA’s “Must See at DAC” list
GSEDA’s “Must See” list

EDA Cafe: Sage to the DRC rescue
Posted on: May 9th, 2013

Declaring itself open for business this week, Sage Design Automation wants to make the world a better place: a) by providing automated design rule closure for advanced process nodes, and b) by lowering the barrier for and broadening the use of design-rule based checking, beyond foundry-provided rules, with a…

Click here to read the full article on edacafe.com


EE Times: Sage solving an orphan EDA problem
Posted on:
May 7th, 2013

Many aspects of the design, verification and manufacturing flows that we use today have evolved over time. Would we have done them that way had we known where it would lead? In many cases probably not, but there was no reasonable way to tell back then, when things got started, what the trajectory…

Click here to read the full article on eetimes.com


iDRM White Paper
Posted on: May 6th, 2013

Fixing the broken interface between design and manufacturing


Press Release: Sage Design Automation launched, with design rule compiler technology and products
Posted on:
May 6th, 2013

iDRM brings automation, ease-of-use, clarity and closure to design rules
iDRM brings automation, ease-of-use, clarity and closure to design rules Santa Clara, California – May 6, 2013 – Sage Design Automation (Sage-DA) has been founded to develop technology and products that automate the rule-based design and verification paradigm. Sage-DA was founded with initial investment from venture capital and angel investors including Alex Shubat, PhD, former… Read more

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